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TDA8933
Class-D audio amplifier
Rev. 01 -- 15 May 2007 Preliminary data sheet
1. General description
The TDA8933 is a high efficiency class-D amplifier with low power dissipation. The continuous time output power is 2 x 10 W in a stereo half bridge application (RL = 8 ) or 1 x 20 W in a mono full bridge application (RL =16 ). Due to the low power dissipation the device can be used without any external heat sink when playing music. Due to the implementation of Thermal Foldback (TF), even for high supply voltages and/or lower load impedances, the device will continue to operate with considerable music output power without the need for an external heat sink. The device has two full differential inputs driving two independent outputs. It can be used in a mono full bridge configuration (Bridge-Tied Load (BTL)) or a stereo half bridge configuration (Single-Ended (SE)).
2. Features
I I I I I I I I I I I I High efficiency Application without heat sink using thermally enhanced small outline package Operating voltage from 10 V to 36 V asymmetrical or 5 V to 18 V symmetrical Thermally protected Thermal foldback Current limiting to avoid audio holes Full short circuit proof to supply lines (using advanced current protection) Switchable internal / external oscillator (master-slave setting) No pop noise Low power dissipation Mono bridge-tied load (full bridge) or stereo single-ended (half bridge) application Full differential inputs
3. Applications
I I I I I I Flat panel television sets Flat panel monitor sets Multimedia systems Wireless speakers Mini/micro systems Home sound sets
NXP Semiconductors
TDA8933
Class-D audio amplifier
4. Quick reference data
Table 1. Quick reference data Conditions asymmetrical supply symmetrical supply IP Iq(tot) supply current total quiescent current RMS output power Sleep mode Operating mode; no load, no snubbers or filter connected continuous time output power per channel RL = 4 ; VP = 17 V THD+N = 0.5 %, fi = 1 kHz THD+N = 0.5 %, fi = 100 Hz THD+N = 10 %, fi = 1 kHz THD+N = 10 %, fi = 100 Hz RL = 8 ; VP = 25 V THD+N = 0.5 %, fi = 1 kHz THD+N = 0.5 %, fi = 100 Hz THD+N = 10 %, fi = 1 kHz THD+N = 10 %, fi = 100 Hz short time output power per channel; THD+N = 10 %, see Figure 23 for details RL = 8 ; VP = 31 V THD+N = 0.5 % THD+N = 10 % 11.2 14.1 12.4 15.7 W W
[2] [1]
Symbol Parameter VP supply voltage
Min 10 5 -
Typ 25 12.5 0.6 40
Max 36 18 1.0 50
Unit V V mA mA
General; Vp = 25 V, fosc = 320 kHz, Tamb = 25 C unless specified otherwise
Stereo SE channel Po(RMS)
5.9 7.5 7.3 9.3 -
6.5 6.5 8.3 8.3 8.1 8.1 10.3 10.3
-
W W W W W W W W
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Preliminary data sheet
Rev. 01 -- 15 May 2007
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NXP Semiconductors
TDA8933
Class-D audio amplifier
Quick reference data ...continued Conditions continuous time output power THD+N = 10 %; fi = 1 kHz RL = 8 ; VP = 17 V THD+N = 0.5 %, fi = 1 kHz THD+N = 0.5 %, fi = 100 Hz THD+N = 10 %, fi = 1 kHz THD+N = 10 %, fi = 100 Hz RL = 16 ; VP = 25 V THD+N = 0.5 %, fi = 1 kHz THD+N = 0.5 %, fi = 100 Hz THD+N = 10 %, fi = 1 kHz THD+N = 10 %, fi = 100 Hz short time output power; THD+N = 10 %, see Figure 35 for details RL = 16 ; VP = 31 V THD+N = 0.5 % THD+N = 10 % 22.8 28.8 25.3 32 W W
[2] [1]
Table 1.
Symbol Parameter Mono BTL channel Po(RMS) RMS output power
Min
Typ
Max
Unit
11.9 15.4 14.9 18.9 -
13.2 13.2 17.1 17.1 16.5 16.5 21 21
-
W W W W W W W W
[1] [2]
Output power is measured indirectly, based on RDSon measurement. 2 layer application board (55 mm x 45 mm), 35 m copper, FR4 base material in free air with natural convection.
5. Ordering information
Table 2. Ordering information Package Name TDA8933T SO32 Description plastic small outline package; 32 leads; body width 7.5 mm Version SOT287-1 Type number
TDA8933_1
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Preliminary data sheet
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NXP Semiconductors
TDA8933
Class-D audio amplifier
6. Block diagram
VDDA 8 OSCREF 10 OSCILLATOR IN1P 2 VSSD PWM MODULATOR CTRL IN1N 3 DRIVER LOW VDDA STABI 11V 12 INREF + VSSP1 VDDA VSSA MANAGER STABI 11V VSSP2 IN2P 15 20 PWM MODULATOR CTRL IN2N 14 DRIVER LOW 23 DRIVER HIGH 22 24 STAB2 25 STAB1 26 DRIVER HIGH OSCIO 31 VDDP1 29 28
BOOT1
27
OUT1 VSSP1
21
BOOT2 VDDP2 OUT2 VSSP2
CGND
7
PROTECTIONS OVP, OCP, OTP UVP, TF, WP
REG5V
18
DREF
DIAG
4 VDDA 6
VSSD 11
HVPREF
POWERUP
30 MODE 5 19 VSSA HALF SUPPLY VOLTAGE CGND 9 13 1, 16, 17, 32
HVP1
ENGAGE
HVP2
010aaa113
VSSA
TEST
VSSD(HW)
Fig 1. Block diagram
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Preliminary data sheet
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NXP Semiconductors
TDA8933
Class-D audio amplifier
7. Pinning information
7.1 Pinning
VSSD(HW) IN1P IN1N DIAG ENGAGE POWER UP CGND VDDA VSSA
1 2 3 4 5 6 7 8 9
32 VSSD(HW) 31 OSCIO 30 HVP1 29 VDDP1 28 BOOT1 27 OUT1 26 VSSP1 25 STAB1 24 STAB2 23 VSSP2 22 OUT2 21 BOOT2 20 VDDP2 19 HVP2 18 DREF 17 VSSD(HW)
010aaa114
TDA8933T SO32
OSCREF 10 HVPREF 11 INREF 12 TEST 13 IN2N 14 IN2P 15 VSSD(HW) 16
Fig 2. Pin configuration diagram
7.2 Pin description
Table 3. Symbol VSSD(HW) IN1P IN1N DIAG ENGAGE POWERUP CGND VDDA VSSA OSCREF HVPREF INREF TEST IN2N IN2P VSSD(HW) VSSD(HW) DREF
TDA8933_1
Pinning description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Description negative digital supply voltage and handle wafer connection positive audio input for channel 1 negative audio input for channel 1 diagnostic output; open-drain engage input to switch between Mute mode and Operating mode power-up input to switch between Sleep mode and Mute mode control ground; reference for POWERUP, ENGAGE and DIAG positive analog supply voltage negative analog supply voltage input internal oscillator setting (only master setting) decoupling of internal half supply voltage reference decoupling for input reference voltage test signal input; for testing purpose only negative audio input for channel 2 positive audio input for channel 2 negative digital supply voltage and handle wafer connection negative digital supply voltage and handle wafer connection decoupling of internal (reference) 5 V regulator for logic supply
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Preliminary data sheet
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TDA8933
Class-D audio amplifier
Pinning description ...continued Pin 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Description half supply output voltage 2 for charging single-ended capacitor for channel 2 positive power supply voltage for channel 2 bootstrap high-side driver channel 2 Pulse Width Modulated (PWM) output channel 2 negative power supply voltage for channel 2 decoupling of internal 11 V regulator for channel 2 drivers decoupling of internal 11 V regulator for channel 1 drivers negative power supply voltage for channel 1 PWM output channel 1 bootstrap capacitor for channel 1 positive power supply voltage for channel 1 half supply output voltage 1 for charging single-ended capacitor for channel 1 oscillator input in slave configuration or oscillator output in master configuration negative digital supply voltage and handle wafer connection
Table 3. Symbol HVP2 VDDP2 BOOT2 OUT2 VSSP2 STAB2 STAB1 VSSP1 OUT1 BOOT1 VDDP1 HVP1 OSCIO VSSD(HW)
8. Functional description
8.1 General
The TDA8933 is a mono full bridge or stereo half bridge audio power amplifier using class-D technology. The audio input signal is converted into a Pulse Width Modulated (PWM) signal via an analog input stage and PWM modulator. To enable the output power Diffusion Metal Oxide Semiconductor (DMOS) transistors to be driven, this digital PWM signal is applied to control and handshake block and driver circuits for both the high side and low side. A 2nd-order-low-pass filter converts the PWM signal to an analog audio signal across the loudspeakers. The TDA8933 contains two independent half bridges with full differential input stages. The loudspeakers can be connected in the following configurations:
* Mono full bridge: Bridge Tied Load (BTL) * Stereo half bridge: Single-Ended (SE)
The TDA8933 contains circuits common to both channels, such as: the oscillator, all reference sources, the mode functionality and a digital timing manager. The following protections are built-in: thermal foldback, temperature, current and voltage.
TDA8933_1
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Preliminary data sheet
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TDA8933
Class-D audio amplifier
8.2 Mode selection and interfacing
The TDA8933 can be switched to one of four operating modes using pins POWERUP and ENGAGE:
* Sleep mode: with low supply current * Mute mode: the amplifiers are switching idle (50 % duty cycle), but the audio signal at
the output is suppressed by disabling the Vl-converter input stages. The capacitors on pins HVP1 and HVP2 have been charged to half the supply voltage (asymmetrical supply only)
* Operating mode: the amplifiers are fully operational with an output signal * Fault mode
Both pins POWERUP and ENGAGE refer to pin CGND. Table 4 shows the different modes as a function of the voltages on the POWERUP and ENGAGE pins.
Table 4. Mode Sleep Mute Operating Fault
[1]
Mode selection for the TDA8933 Pin POWERUP[1] < 0.8 V 2 V to 6 V 2 V to 6 V 2 V to 6 V ENGAGE[1] < 0.8 V < 0.8 V 3 V to 6 V undefined DIAG undefined >2V >2V < 0.8 V
When there are symmetrical supply conditions, the voltage applied to pins POWERUP and ENGAGE must never exceed the supply voltage (VDDA, VDDP1 or VDDP2).
If the transition between Mute mode and Operating mode is controlled via a time constant, the start-up will be pop free since the DC output offset voltage is applied gradually to the output between Mute mode and Operating mode. The bias current setting of the VI-converters is related to the voltage on pin ENGAGE.
* Mute mode: the bias current setting of the VI-converters is zero (VI-converters
disabled).
* Operating mode: the bias current is at maximum.
The time constant required to apply the DC output offset voltage gradually between Mute mode and Operating mode can be generated by applying a decoupling capacitor on pin ENGAGE. The value of the capacitor on pin ENGAGE should be 470 nF.
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Preliminary data sheet
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NXP Semiconductors
TDA8933
Class-D audio amplifier
VP
POWERUP
DREF
HVPREF
HVP1, HVP2 0.43VENGAGE ENGAGE 0.3VENGAGE
0.17VENGAGE
audio OUT1, OUT2 PWM
AUDIO
AUDIO
AUDIO
PWM
PWM
DIAG
OSCIO operating mute operating fault operating sleep
001aae788
Fig 3. Start-up sequence
8.3 Pulse width modulation frequency
The output signal of the amplifier is a PWM signal with a carrier frequency of approximately 320 kHz. Using a 2nd-order-low-pass filter in the application results in an analog audio signal across the loudspeaker. The PWM switching frequency can be set by an external resistor Rosc connected between pin OSCREF and VSSD(HW). The carrier frequency can be set between 300 kHz and 500 kHz. Using an external resistor of 39 k, the carrier frequency is set to an optimized value of 320 kHz (see Figure 4). If two or more TDA8933 devices are used in the same audio application, it is recommended to synchronize the switching frequency of all devices.This can be done by connecting all the OSCIO pins together and configuring one of the TDA8933 devices in the application as the clock master. Configure the other TDA8933 devices as slaves. Pin OSCIO is a 3-state input or output buffer. Pin OSCIO is configured in master mode as oscillator output, and in slave mode as oscillator input. Master mode is enabled by applying a resistor between pin OSCREF and VSSD(HW), while slave mode is enabled by connecting pin OSCREF directly to VSSD(HW) (without any resistor). The value of the resistor also sets the frequency of the carrier and can be calculated with Equation 1:
TDA8933_1
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Preliminary data sheet
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TDA8933
Class-D audio amplifier
9
12.45x10 f osc = -----------------------R osc Where:
(1)
fosc = oscillator frequency (Hz) Rosc = oscillator resistor () (on pin OSCREF)
001aad758
550 fosc (kHz) 450
350
250 25 30 35 40 Rosc (k) 45
Fig 4. Oscillation frequency as a function of Rosc
Table 5 summarizes how to configure the TDA8933 in master or slave configuration.
Table 5. Master/slave configuration Pin OSCREF Master Slave Rosc > 25 k to VSSD(HW) Rosc = 0 ; shorted to VSSD(HW) OSCIO output input
Configuration
8.4 Protections
The following protections are implemented in the TDA8933:
* * * * *
Thermal Foldback (TF) OverTemperature Protection (OTP) OverCurrent Protection (OCP) Window Protection (WP) Supply voltage protections - UnderVoltage Protection (UVP) - OverVoltage Protection (OVP) - UnBalance Protection (UBP)
* ElectroStatic Discharge (ESD)
The behavior of the device under the different fault conditions differs according to the protection activated and is described in the following sections.
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Preliminary data sheet
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NXP Semiconductors
TDA8933
Class-D audio amplifier
8.4.1 Thermal Foldback (TF)
If the junction temperature of the TDA8933 exceeds the threshold level (Tj > 140 C), the gain of the amplifier is decreased gradually to a level where the combination of dissipation (P) and the thermal resistance from junction to ambient (Rth(j-a)) results in a junction temperature around the threshold level. This means that the device will not switch off completely, but remains operational at lower output power levels. With music output signals, this feature enables high peak output powers while still operating without any external heat sink other than the printed-circuit board area. If the junction temperature still increases due to external causes, the OverTemperature Protection (OTP) shuts down the amplifier completely.
8.4.2 OverTemperature Protection (OTP)
If the junction temperature Tj > 155 C, the power stage will shut down immediately.
8.4.3 OverCurrent Protection (OCP)
When the output current of the device exceeds 2 A due to a short-circuit across the load or an impedance drop, the cycle-by-cycle current limitation becomes active. This means the device will not switch off, but continue to operate while limiting the current without causing audio holes (interruptions). The maximum output current will not go beyond the absolute maximum current. If the current exceeds 2 A due to a low ohmic short from the demodulated output (after the inductor) to either VSS or VDD both power stages become floating. The DIAG is set low for 50 ms and the internal timer of 100 ms is started. The timer will keep both power stages disabled for 100 ms. As long as the short remains, this cycle will repeat. The average power dissipation in the TDA8933 will be low because the short-circuit current will flow only during a very small part of the timer cycle of 100 ms.
8.4.4 Window Protection (WP)
WP checks the PWM output voltage before switching from Sleep mode to Mute mode (outputs switching) and is activated:
* During the start-up sequence, when pin POWERUP is switched from Sleep mode to
Mute mode. In the event of a short-circuit at one of the output terminals to VDDP1, VSSP1, VDDP2 or VSSP2 the start-up procedure is interrupted and the TDA8933 waits for open-circuit outputs. Because the check is done before enabling the power stages, no large currents will flow in the event of a short-circuit.
* When the amplifier is shut down completely, due to activation of the OCP because a
short to one of the supply lines is made, then during restart (after 100 ms) the window protection will be activated. As a result, the amplifier will not start up until the short to the supply lines is removed.
8.4.5 Supply voltage protections
If the supply voltage drops below 10 V, the UVP circuit is activated and the system will shut down directly. This switch-off will be silent and without pop noise. When the supply voltage rises above the threshold level, the system is restarted again after 100 ms.
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Preliminary data sheet
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NXP Semiconductors
TDA8933
Class-D audio amplifier
If the supply voltage exceeds 36 V, the OVP circuit is activated and the power stages will shut down. It is re-enabled as soon as the supply voltage drops below the threshold level. The system is restarted again after 100 ms. It should be noted that supply voltages > 40 V may damage the TDA8933. Two conditions should be distinguished:
* If the supply voltage is pumped to higher values by the TDA8933 application itself
(see also Section 14.8), the OVP is triggered and the TDA8933 is shut down. The supply voltage will decrease and the TDA8933 is protected against any overstress.
* If a supply voltage > 40 V is caused by other or external causes, the TDA8933 will
shut down, but the device can still be damaged since the supply voltage will remain > 40 V in this case. The OVP protection is not a supply clamp. An additional UBP circuit compares the positive analog supply voltage (VDDA) and the negative analog supply voltage (VSSA) and is triggered if the voltage difference between them exceeds a certain level. This level depends on the sum of both supply voltages. The unbalance threshold levels can be defined as follows:
* LOW-level threshold: VP(th)(ubp)l < 8/5 x VHVPREF * HIGH-level threshold: VP(th)(ubp)h > 8/3 x VHVPREF
In a symmetrical supply the UBP is released when the unbalance of the supply voltage is within 6 % of its starting value. Table 6 shows an overview of all protections and the effect on the output signal.
Table 6. Protection OTP OCP WP UVP OVP UBP Overview of protections for the TDA8933 Restart When fault is removed no yes yes no no no Every 100 ms yes no no yes yes yes
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TDA8933
Class-D audio amplifier
8.5 Diagnostic input and output
Whenever one of the protections is triggered, except for TF, pin DIAG is activated to LOW level (see Table 6). An internal reference supply will pull up the open-drain DIAG output to approximately 2.4 V. This internal reference supply can deliver approximately 50 A. The DIAG pin refers to pin CGND.The diagnostic output signal during different short circuit conditions is illustrated in Figure 5. Using pin DIAG as input, a voltage < 0.8 V will put the device into Fault mode.
Vo 2.4 V
Vo 2.4 V
amplifier restart 0V 50 ms 50 ms shorted load 0V
no restart short to supply line
001aad759
Fig 5. Diagnostic output for different kinds of short circuit conditions
8.6 Differential inputs
For a high common-mode rejection ratio and for maximum flexibility in the application, the audio inputs are fully differential. By connecting the inputs anti-parallel, the phase of one of the two channels can be inverted, so that the amplifier can operate as a mono BTL amplifier. The input configuration for a mono BTL application is illustrated in Figure 6. In the single-ended configuration it is also recommended to connect the two differential inputs in anti-phase. This has advantages for the current handling of the power supply at low signal frequencies and minimizes supply pumping (see also Section 14.8).
IN1P IN1N audio input
OUT1
IN2P IN2N
OUT2
001aad760
Fig 6. Input configuration for a mono BTL application
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TDA8933
Class-D audio amplifier
8.7 Output voltage buffers
When pin POWERUP is set HIGH, the half supply output voltage buffers are switched on in asymmetrical supply configuration. The start-up will be pop free because the device starts switching when the capacitor on pin HVPREF and the SE capacitors are completely charged. Output voltage buffers:
* Pins HVP1 and HVP2: The time required for charging the SE capacitor depends on its
value. The half supply voltage output is disabled when the TDA8933 is used in a symmetrical supply application.
* Pin HVPREF: This output voltage reference buffer charges the capacitor on pin
HVPREF.
* Pin INREF: This output voltage reference buffer charges the input reference capacitor
on pin INREF. Pin INREF applies the bias voltage for the inputs.
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TDA8933
Class-D audio amplifier
9. Internal circuitry
Table 7. Pin Internal circuitry Symbol Equivalent circuit
1, 16, 17, 32 VDDA
1, 16, 17, 32 VSSD(HW)
VSSA 001aad784
2 3 12 14 15
IN1P IN1N INREF IN2N IN2P
VDDA
13
VSSA 001aad795
4
DIAG
VDDA 2.5 V
50 A
4
5 k 20 %
VSSA
CGND
010aaa198
5
ENGAGE
VDDA 4.6 V Iref = 20 A 5
226 k 20 %
VSSA CGND
001aad787
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TDA8933
Class-D audio amplifier
Internal circuitry ...continued Symbol POWERUP
VDDA
Table 7. Pin 6
Equivalent circuit
6
VSSA
CGND
001aad788
7
CGND
VDDA
7
VSSA 001aad789
8
VDDA
8
VSSA
VSSD 001aad790
9
VSSA
VDDA
9
VSSD 001aad791
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TDA8933
Class-D audio amplifier
Internal circuitry ...continued Symbol OSCREF
VDDA Iref 10
Table 7. Pin 10
Equivalent circuit
VSSA
001aad792
11
HVPREF
VDDA
11
VSSA
010aaa199
13
TEST
VDDA
13
VSSA 001aad795
18
DREF
VDD
18
VSSD 010aaa200
19 30
HVP2 HVP1
VDDA
19, 30
VSSA
010aaa201
20 23 26 29
VDDP2 VSSP2 VSSP1 VDDP1
23, 26
001aad798
20, 29
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Class-D audio amplifier
Internal circuitry ...continued Symbol BOOT2 BOOT1
21, 28
Table 7. Pin 21 28
Equivalent circuit
OUT1, OUT2
001aad799
22 27
OUT2 OUT1
VDDP1, VDDP2
22, 27
VSSP1, VSSP2
010aaa202
24 25
STAB2 STAB1
24, 25 VDDA
VSSP1, VSSP2
010aaa203
31
OSCIO
DREF
31 VSSD 010aaa204
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Class-D audio amplifier
10. Limiting values
Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VP Vx Parameter supply voltage voltage on pin x IN1P, IN1N, IN2P, IN2N OSCREF, OSCIO, TEST POWERUP, ENGAGE, DIAG all other pins IORM Tj Tstg Tamb P
[1] [2] [3] [4] [5]
[1] [2] [3]
Conditions asymmetrical supply
Min -0.3 -5 VCGND - 0.3 VSS - 0.3 2.3 -55 -40 -
Max +40 +5 6
Unit V V V V
VSSD(HW) - 0.3 5
[4]
VDD + 0.3 V 150 +150 +85 5 A C C C W
repetitive peak output current junction temperature storage temperature ambient temperature power dissipation
maximum output current limiting
[5]
Measured with respect to pin INREF; Vx < VDD + 0.3 V. Measured with respect to pin VSSD(HW); Vx < VDD + 0.3 V. Measured with respect to pin CGND; Vx < VDD + 0.3 V. VSS = VSSP1 = VSSP2; VDD = VDDP1 = VDDP2. Current limiting concept.
11. Thermal characteristics
Table 9. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions free air natural convection JEDEC test board 2 layer application board j-lead thermal characterization parameter from junction to lead thermal characterization parameter from junction to top of package
[3] [1] [2]
Min -
Typ 41 44 -
Max 44 30
Unit K/W K/W K/W
j-top
-
-
8
K/W
[1] [2] [3]
Measured in a JEDEC high K-factor test board (standard EIA/JESD 51-7) in free air with natural convection. 2 layer application board (55 mm x 45 mm), 35 m copper, FR4 base material in free air with natural convection. Strongly dependent on where the measurement is taken on the package.
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TDA8933
Class-D audio amplifier
12. Static characteristics
Table 10. Characteristics VP = 25 V, fosc = 320 kHz and Tamb = 25 C; unless specified otherwise. Symbol Supply VP IP Iq(tot) supply voltage supply current total quiescent current asymmetrical supply symmetrical supply Sleep mode Operating mode; no load, no snubbers or filter connected Tj = 25 C Tj = 125 C 10 5 25 12.5 0.6 40 36 18 1.0 50 V V mA mA Parameter Conditions Min Typ Max Unit
Series resistance output switches RDSon drain-source on-state resistance 0 VI = 3 V 0 2 4.2 0 VI = 3 V 0 3 protection activated; see Table 6 Operating mode Bias voltage for inputs: pin INREF VO(bias) bias output voltage Reference to VSSA 2.1 V Half supply voltage Pins HVP1 and HVP2 VO IO Pin HVPREF VO output voltage half supply reference voltage in Mute mode 0.5VP - 0.2 V 4.5 0.5VP 0.5VP + 0.2 V 5.1 V output voltage output current half supply voltage to charge SE capacitor VHVP1 = VHVP2 = VO - 1 V 0.5VP - 0.2 V 0.5VP 50 0.5VP + 0.2 V V mA 2 350 545 1 4.6 20 2.5 6.0 20 0.8 6.0 5.0 6.0 40 0.8 6.0 0.8 3.3 m m V A V V V V A V V V V
Power up input: pin POWERUP[1] VI II VIL VIH VO VI IO VIL VIH VO input voltage input current LOW-level input voltage HIGH-level input voltage ENGAGE[1] output voltage input voltage output current LOW-level input voltage HIGH-level input voltage DIAG[1] output voltage
Engage input: pin
Diagnostic output: pin
Reference voltage for internal logic: pin DREF VO output voltage 4.8 V
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Preliminary data sheet
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TDA8933
Class-D audio amplifier
Table 10. Characteristics ...continued VP = 25 V, fosc = 320 kHz and Tamb = 25 C; unless specified otherwise. Symbol VO(offset) Parameter output offset voltage Conditions SE; with respect to HVPREF Mute mode Operating mode BTL Mute mode Operating mode Stabilizer output: pins STAB1, STAB2 VO output voltage Mute mode and Operating mode; with respect to pins VSSP1 and VSSP2 10 11 12 V 20 150 mV mV 15 100 mV mV Min Typ Max Unit Amplifier outputs: pins OUT1 and OUT2
Voltage protections VP(uvp) VP(ovp) VP(th)(ubp)l VP(th)(ubp)h undervoltage protection supply voltage overvoltage protection supply voltage low unbalance protection threshold supply voltage high unbalance protection threshold supply voltage overcurrent protection output current thermal protection activation temperature thermal foldback activation temperature HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage maximum number of slaves driven by one master VHVPREF = 11 V VHVPREF = 11 V 8.0 36.1 29 9.5 38.5 9.9 40 18 V V V V
Current protections IO(ocp) current limiting 2.0 2.3 A
Temperature protection Tact(th_prot) Tact(th_fold) 155 140 160 150 C C
Oscillator reference: pin OSCIO[2] VIH VIL VOH VOL Nslave(max)
[1] [2]
4.0 0 4.0 0 12
-
5.0 0.8 5.0 0.8 -
V V V V -
Measured with respect to pin CGND. Measured with respect to pin VSSD(HW).
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TDA8933
Class-D audio amplifier
13. Dynamic characteristics
Table 11. Switching characteristics VP = 25 V; Tamb = 25 C; unless otherwise specified. Symbol fosc Parameter oscillator frequency Conditions Rosc = 39 k range Timing PWM output: pins OUT1 and OUT2 tr tf tw(min) rise time fall time minimum pulse width IO = 0 A IO = 0 A IO = 0 A 10 10 80 ns ns ns Min 300 Typ 320 Max 500 Unit kHz kHz Internal oscillator
Table 12. SE characteristics VP = 25 V, RL = 2 x 8 , fi = 1 kHz, fosc = 320 kHz, RS < 0.1 [6] and Tamb = 25 C; unless otherwise specified. Symbol Po(RMS) Parameter RMS output power Conditions continuous time output power per channel RL = 4 ; VP = 17 V THD+N = 0.5 %, fi = 1 kHz THD+N = 0.5 %, fi = 100 Hz THD+N = 10 %, fi = 1 kHz THD+N = 10 %, fi = 100 Hz RL = 8 ; VP = 25 V THD+N = 0.5 %, fi = 1 kHz THD+N = 0.5 %, fi = 100 Hz THD+N = 10 %, fi = 1 kHz THD+N = 10 %, fi = 100 Hz short time output power per channel; THD+N = 10 %, see Figure 23 for details RL = 8 ; VP = 31 V THD+N = 0.5 % THD+N = 10 % THD+N total harmonic distortion-plus-noise Po = 1 W fi = 1 kHz fi = 6 kHz Gv(cl) |GV| cs SVRR closed-loop voltage gain voltage gain difference channel separation supply voltage ripple rejection Po = 1 W; fi = 1 kHz Operating mode fi = 100 Hz fi = 1 kHz |Zi|
TDA8933_1
Min
[1]
Typ
Max
Unit
5.9 7.5 7.3 9.3 [2]
6.5 6.5 8.3 8.3 8.1 8.1 10.3 10.3
-
W W W W W W W W
11.2 14.1
[3]
12.4 15.7 0.011 0.06 30 0.5 80 60 50 100
0.1 0.1 31 1 -
W W % % dB dB dB dB dB k
29 70
[4]
Vi =100 mV; no load
40 70
input impedance
differential
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TDA8933
Class-D audio amplifier
Table 12. SE characteristics ...continued VP = 25 V, RL = 2 x 8 , fi = 1 kHz, fosc = 320 kHz, RS < 0.1 [6] and Tamb = 25 C; unless otherwise specified. Symbol Vn(o) VO(mute) CMRR po Parameter noise output voltage mute output voltage common mode rejection ratio output power efficiency Conditions Operating mode; Rs = 0 Mute mode Mute mode; Vi = 1 V (RMS) and fi = 1 kHz Vi(cm) = 1 V (RMS) Po = 10 W VP = 17 V; RL = 4 VP = 25 V; RL = 8
[1] [2] [3] [4] [5] [6] Output power is measured indirectly; based on RDSon measurement. 2 layer application board (55 mm x 45 mm), 35 m copper, FR4 base material in free air with natural convection. THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall. Maximum Vripple = 2 V (p-p); RS = 0 . B = 20 Hz to 20 kHz, AES17 brick wall. RS is the series resistance of inductor and capacitor of low-pass LC filter in the application.
[5] [5]
Min -
Typ 100 70 100 75
Max 150 100 -
Unit V V V dB
86 89
87 90
-
% %
Table 13. BTL characteristics VP = 25 V, RL = 16 , fi = 1 kHz, fosc = 320 kHz, RS < 0.1 [5] and Tamb = 25 C; unless otherwise specified. Symbol Po(RMS) Parameter RMS output power Conditions continuous time output power: THD+N = 10 %; fi = 1 kHz RL = 8 ; VP = 17 V THD+N = 0.5 %, fi = 1 kHz THD+N = 0.5 %, fi = 100 Hz THD+N = 10 %, fi = 1 kHz THD+N = 10 %, fi = 100 Hz RL = 16 ; VP = 25 V THD+N = 0.5 %, fi = 1 kHz THD+N = 0.5 %, fi = 100 Hz THD+N = 10 %, fi = 1 kHz THD+N = 10 %, fi = 100 Hz short time output power; THD+N = 10 %, see Figure 35 for details RL = 16 ; VP = 31 V THD+N = 0.5 % THD+N = 10 % THD+N total harmonic distortion-plus-noise Po = 1 W fi = 1 kHz fi = 10 kHz Gv(cl) |Zi| closed-loop voltage gain input impedance differential
[3] [2] [1]
Min
Typ
Max
Unit
11.9 15.4 14.9 18.9 -
13.2 13.2 17.1 17.1 16.5 16.5 21 21
-
W W W W W W W W
22.8 28.8 35 35
25.3 32 0.04 0.18 36 50
0.1 0.24 37 -
W W % % dB k
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NXP Semiconductors
TDA8933
Class-D audio amplifier
Table 13. BTL characteristics ...continued VP = 25 V, RL = 16 , fi = 1 kHz, fosc = 320 kHz, RS < 0.1 [5] and Tamb = 25 C; unless otherwise specified. Symbol Vn(o) Parameter noise output voltage Conditions Rs = 0 Operating mode Mute mode VO(mute) CMRR po mute output voltage common mode rejection ratio output power efficiency Mute mode; Vi = 1 V (RMS) and fi = 1 kHz Vi(cm) = 1 V (RMS) Po = 17 W; VP = 17 V; RL = 8 Po = 21 W; VP = 25 V; RL = 16
[1] [2] [3] [4] [5] Output power is measured indirectly; based on RDSon measurement. 2 layer application board (55 mm x 45 mm), 35 m copper, FR4 base material in free air with natural convection. THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall. B = 22 Hz to 20 kHz, AES17 brick wall. RS is the series resistance of inductor and capacitor of low-pass LC filter in the application.
[4] [4]
Min 87 90
Typ 100 70 100 75 89 92
Max 150 100 -
Unit V V V dB % %
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TDA8933
Class-D audio amplifier
14. Application information
14.1 Output power estimation
The output power Po at THD+N = 0.5 %, just before clipping, for the SE and BTL configurations can be estimated using Equation 2 and Equation 3. SE configuration:
2 RL ---------------------------------------------------------- x ( 1 - t x f osc ) x V P w ( min ) R L + R DSon + R s + R ESR = -----------------------------------------------------------------------------------------------------------------------------------------8 x RL
P o ( 0.5
%)
(2)
BTL configuration:
2 RL ------------------------------------------------------ x ( 1 - t w ( min ) x f osc ) x V P R L + 2 x ( R DSon + R s ) = -------------------------------------------------------------------------------------------------------------------------------------2 x RL
P o ( 0.5
%)
(3)
Where: VP = supply voltage VDDP1 - VSSP1 (V) or VDDP2 - VSSP2 (V) RL = load resistance () RDSon = drain-source on-state resistance () Rs = series resistance output inductor () RESR = equivalent series resistance SE capacitance () tw(min) = minimum pulse width (s); 80 ns typical fosc = oscillator frequency (Hz); 320 kHz typical with Rosc = 39 k The output power Po at THD+N = 10 % can be estimated by: P o ( 10
%)
= 1.25 x P o ( 0.5
%)
(4)
Figure 7 and Figure 8 show the estimated output power at THD+N = 0.5 % and THD+N = 10 % as a function of the supply voltage for SE and BTL configurations at different load impedances. The output power is calculated with: RDSon = 0.35 (at Tj = 25 C), Rs = 0.05 , RESR = 0.05 and IO(ocp) = 2 A (minimum).
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TDA8933
Class-D audio amplifier
20 Po (W) 16
010aaa143
20 Po (W) 15
010aaa147
RL = 8
RL = 8
12
RL = 6 10
RL = 6
8
RL = 4 5
RL = 4
4
0 10 16 22 28 VP (V) 34
0 10 20 30 VP (V) 36
a. THD+N = 0.5 %
b. THD+N = 10 %
(1) When the maximum current of 2 A is reached, the current limitation feature becomes active. See also Section 8.4.3 for OCP details.
Fig 7. SE output power as a function of supply voltage
40 Po (W) 30
010aaa144
40 Po (W) 30
010aaa145
RL = 16
RL = 16
20 RL = 8 RL = 6 10
20 RL = 6 10
RL = 8
0 10 20 30 VP (V) 40
0 10 20 30 VP (V) 40
a. THD+N = 0.5 %
b. THD+N = 10 %
(1) When the maximum current of 2 A is reached, the current limitation feature becomes active. See also Section 8.4.3 for OCP details.
Fig 8. BTL output power as a function of supply voltage
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Class-D audio amplifier
14.2 Output current limiting
The peak output current IOM is internally limited to 2 A (minimum). During normal operation the output current should not exceed this threshold level, otherwise the signal is distorted. The peak output current in SE or BTL configurations can be calculated using Equation 5 and Equation 6. SE configuration: 0.5 x V P I O ( max ) ---------------------------------------------------------- 2 A R L + R DSon + R s + R ESR BTL configuration: VP I O ( max ) ----------------------------------------------------- 2 A R L + 2 x ( R DSon + R s ) Where: VP = supply voltage VDDP1 - VSSP1 (V) or VDDP2 - VSSP2 (V) RL = load resistance () RDSon = drain-source on-state resistance () Rs = series resistance () RESR = equivalent series resistance SE capacitance () Example: An 8 speaker in the BTL configuration can be used up to a supply voltage of 18 V without running into current limiting. Current limiting (clipping) will avoid audio holes but produces a similar distortion to voltage clipping. (6) (5)
14.3 Speaker configuration and impedance
For a flat frequency response (second order Butterworth filter) it is necessary to change the low-pass filter components LLC and CLC according to the speaker configuration and impedance. Table 14 shows the required values in practice.
Table 14. SE Filter component values RL () 4 6 8 BTL 8 16 LLC (H) 22 33 47 22 47 CLC (nF) 680 470 330 680 330
Configuration
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TDA8933
Class-D audio amplifier
14.4 Single-ended capacitor
The SE capacitor forms a high-pass filter with the speaker impedance. So the frequency response will roll off with 20 dB per decade below f-3dB (3 dB cut-off frequency). The 3 dB cut-off frequency is equal to: 1 f -3dB = ---------------------------------2 x R L x C SE Where: f-3dB = 3 dB cut-off frequency (Hz) RL = load resistance () CSE = single-ended capacitance (F); see Figure 37. Table 15 shows an overview of the required SE capacitor values in the case of 60 Hz, 40 Hz or 20 Hz 3 dB cut-off frequency.
Table 15. SE capacitor values CSE (F) f-3dB = 60 Hz 4 6 8 680 470 330 f-3dB = 40 Hz 1000 680 470 f-3dB = 20 Hz 2200 1500 1000
(7)
Impedance ()
14.5 Gain reduction
The gain of the TDA8933 is internally fixed at 30 dB for SE, and 36 dB for BTL. The gain can be reduced by a resistive voltage divider at the input (see Figure 9).
R1
470 nF R3 100 k
audio in
R2 470 nF
010aaa137
Fig 9. Input configuration for reducing gain
When applying a resistive divider, the total voltage gain Gv(tot) can be calculated using Equation 8 and Equation 9: R EQ G v ( tot ) = G v ( cl ) + 20 log ----------------------------------------R EQ + ( R1 + R2 ) Where: Gv(tot) = total voltage gain (dB) Gv(cl) = closed-loop voltage gain, fixed at 30 dB for SE (dB) REQ = equivalent resistance, R3 and Zi ()
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TDA8933
Class-D audio amplifier
R1 = series resistors () R2 = series resistors () R3 x Z R EQ = -----------------i R3 + Z i Where: REQ = equivalent resistance () R3 = parallel resistor () Zi = internal input impedance () Example: Substituting R1 = R2 = 4.7 k, Zi = 100 k and R3 = 22 k in Equation 8 and Equation 9 results in a gain of Gv(tot) = 26.3 dB. (9)
14.6 Device synchronization
If two or more TDA8933 devices are used in one application it is recommended that all devices are synchronized at the same switching frequency to avoid beat tones. Synchronization can be realized by connecting all OSCIO pins together and configuring one of the TDA8933 devices as master, while the other TDA8933 devices are configured as slaves (see Figure 10). A device is configured as master when a resistor Rosc is connected between pin OSCREF and pin VSSD(HW), setting the carrier frequency. Pin OSCIO of the master is then configured as an oscillator output for synchronization. The OSCREF pins of the slave devices should be shorted to pin VSSD(HW), configuring pin OSCIO as an input.
master IC1 slave IC2
TDA8933
OSCREF VSSD(HW) OSCIO
TDA8933
OSCIO VSSD(HW) OSCREF
Cosc 100 nF
Rosc 39 k
010aaa138
Fig 10. Master/slave concept in two-chip application
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TDA8933
Class-D audio amplifier
14.7 Thermal behavior (printed-circuit board considerations)
The heat sink in an application with a TDA8933 is made using the copper on the printed-circuit board. The TDA8933 uses the four corner leads (pins 1, 16, 17 and 32) for heat transfer from the die to the PCB. The thermal foldback will limit the maximum junction temperature to 140 C. Equation 10 shows the relation between the maximum allowable power dissipation P and the thermal resistance from junction to ambient. T j ( max ) - T amb R th ( j - a ) = ----------------------------------P Where: Rth(j-a) = thermal resistance from junction to ambient (K/W) Tj(max) = maximum junction temperature (C) Tamb = ambient temperature (C) P = power dissipation (W), which is determined by the efficiency of the TDA8933 The power dissipation is shown in Figure 21 (SE) and Figure 33 (BTL). The thermal resistance, Rth(j-a), of a 2 layer application board (55 mm x 45 mm), 35 m copper, FR4 base material in free air with natural convection, is 44 K/W (typ.). (10)
14.8 Pumping effects
When the amplifier is used in an SE configuration, a so-called `pumping effect' can occur. During one switching interval, energy is taken from one supply (e.g. VDDP1), while a part of that energy is delivered back to the other supply line (e.g. VSSP1), and vice versa. When the power supply cannot sink energy, the voltage across the output capacitors of that power supply will increase. The voltage increase caused by the pumping effect depends on:
* * * * *
Speaker impedance Supply voltage Audio signal frequency Value of decoupling capacitors on supply lines Source and sink currents of other channels
The pumping effect should not cause a malfunction of either the audio amplifier or the power supply. For instance, this malfunction can be caused by triggering of the undervoltage or overvoltage protection of the amplifier. Pumping effects in an SE configuration can be minimized by connecting audio inputs in anti-phase and changing the polarity of one speaker, as shown in Figure 11.
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TDA8933
Class-D audio amplifier
IN1P audio in1 OUT1 IN1N
IN2N audio in2 OUT2 IN2P
010aaa140
Fig 11. SE application for reducing pumping effect
14.9 SE curves measured in the reference design
102 THD+N (%) 10
010aaa158
1
10-1
(1) (3)
10-2
(2)
10-3 10-2
10-1
1
10 Po (W/channel)
102
(1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz
a. VP = 25 V; RL = 2 x 8 Fig 12. Total harmonic distortion-plus-noise as a function of output power
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TDA8933
Class-D audio amplifier
102 THD+N (%) 10
010aaa156
1
10-1
(1) (3)
10-2
(2)
10-3 10-2
10-1
1
10 Po (W/channel)
102
(1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz
a. VP = 17 V; RL = 2 x 4 Fig 13. Total harmonic distortion-plus-noise as a function of output power
102 THD+N (%) 10
010aaa159
1
(1) (2)
10-1
10-2
10-3 10
102
103
104 fi (Hz)
105
(1) Po = 7 W (2) Po = 1 W
a. VP = 25 V; RL = 2 x 8 Fig 14. Total harmonic distortion-plus-noise as a function of frequency
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TDA8933
Class-D audio amplifier
102 THD+N (%) 10
010aaa160
1
(1) (2)
10-1
10-2
10-3 10
102
103
104 fi (Hz)
105
(1) Po = 5 W (2) Po = 1 W
a. VP = 17 V; RL = 2 x 4 Fig 15. Total harmonic distortion-plus-noise as a function of frequency
35 Gv (dB) 30
010aaa146
0 SVRR (dB) -20
010aaa155
(2)
25
(1)
-40
(2)
20
-60 (1) 15
10 10
102
103
104 fi (Hz)
105
-80 10
102
103
104 fi (Hz)
105
Po = 1 W (RMS) (1) VP = 17 V; RL = 2 x 4 ; CSE = 1000 F (2) VP = 25 V; RL = 2 x 8 ; CSE = 1000 F
Vripple = 500 mV (RMS) referenced to ground; Ri = 0 (shorted input) (1) VP = 17 V; RL = 2 x 4 (2) VP = 25 V; RL = 2 x 8
Fig 16. Gain as a function of frequency
Fig 17. Supply voltage ripple rejection as a function of frequency
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TDA8933
Class-D audio amplifier
120 S/N (dB) 80
010aaa148
-20 cs (dB) -40
010aaa153
-60
(1)
40 -80
(2)
0 10-2
10-1
1
10 102 Po (W/channel)
-100 10
102
103
104 fi (Hz)
105
Ri = 0 ; 20 kHz brick wall filter AES17 (1) RL = 2 x 4 ; VP = 17 V (2) RL = 2 x 8 ; VP = 25 V
Po = 1 W; CHVPREF = 47 F (1) VP = 17 V; RL = 2 x 4 (2) VP = 25 V; RL = 2 x 8
Fig 18. Signal-to-noise ratio as a function of output power
Fig 19. Channel separation as a function of frequency
100 po (%) 75
(1)
010aaa149
(2)
3.0 P (W) 2.0
010aaa152
(1) (2)
50
1.0
25
0.0 10-2
10-1
1
10 102 Po (W/channel)
0 0 5 10 15 Po (W/channel)
po = (2 x Po) / (2 x Po + P) (1) VP = 17 V; RL = 2 x 4 ; fi = 1 kHz (2) VP = 25 V; RL = 2 x 8 ; fi = 1 kHz
Power dissipation in junction only. (1) VP = 17 V; RL = 2 x 4 ; fi = 1 kHz (2) VP = 25 V; RL = 2 x 8 ; fi = 1 kHz
Fig 20. Output power efficiency as a function of output power
Fig 21. Power dissipation as a function of output power per channel (two channels driven)
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TDA8933
Class-D audio amplifier
20 Po (W) 15
(1) (2)
010aaa206
5.0 P (W) 4.0
(2)
010aaa207
3.0
(1)
10
(3) (4)
2.0
5 1.0
0 10 20 30 VP (V) 40
0.0 10 18 26 34 VP (V) 42
fi = 1 kHz (1) RL = 2 x 8 SE; THD = 10 % (2) RL = 2 x 8 SE; THD = 0.5 % (3) RL = 2 x 4 SE; THD = 10 % (4) RL = 2 x 4 SE; THD = 0.5 %
fi = 1 kHz; power dissipation in junction only; short time PO at THD+N = 10 % (1) RL = 2 x 4 SE (2) RL = 2 x 8 SE
Fig 22. Output power per channel as a function of supply voltage
Fig 23. Power dissipation as a function of supply voltage
20 Po (W/channel) 16
(2)
010aaa205
10 Po (W/channel) 8
(1)
010aaa229
12
(1)
6
8
4
4
2
0 0 150 300 450 time (s) 600
0 0 150 300 450 time (s) 600
(1) VP = 25 V (2) VP = 31 V 2 layer application board (55 mm x 45 mm), 35 copper, FR4 base material in free air with natural convection.
(1) VP = 17 V
a. RL = 2 x 8 SE; fi = 1 kHz Fig 24. Output power as a function of time
b. RL = 2 x 4 SE; fi = 1 kHz
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Class-D audio amplifier
4 Vo (V) OPERATING 3
010aaa227
2
1
SLEEP 0 0 0.5 1 1.5 2 2.5 3 VPOWERUP (V)
fi = 1 kHz; Vi = 100 mV; VENGAGE > 3 V
Fig 25. Output voltage as a function of voltage on pin POWERUP
4 Vo (V) 3 OPERATING
010aaa228
2
1
MUTE 0 0 0.5 1 1.5 2 2.5 3 VENGAGE (V)
fi = 1 kHz; Vi = 100 mV
Fig 26. Output voltage as a function of voltage on pin ENGAGE
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TDA8933
Class-D audio amplifier
14.10 BTL curves measured in the reference design
102 THD+N (%) 10
010aaa157
1
10-1
(1)
10-2
(2) (3)
10-3 10-2
10-1
1
10 Po (W)
102
(1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz
a. VP = 17 V; RL = 8 Fig 27. Total harmonic distortion-plus-noise as a function of output power
102 THD+N (%) 10
010aaa161
1
(1)
10-1
(2)
10-2
(3)
10-3 10-2
10-1
1
10 Po (W)
102
(1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz
a. VP = 25 V; RL = 16 Fig 28. Total harmonic distortion-plus-noise as a function of output power
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TDA8933
Class-D audio amplifier
102 THD+N (%) 10
010aaa162
1
10-1
(1)
10-2
(2)
10-3 10
102
103
104 fi (Hz)
105
(1) Po = 10 W (2) Po = 1 W
a. VP = 17 V; RL = 8 Fig 29. Total harmonic distortion-plus-noise as a function of frequency
102 THD+N (%) 10
010aaa163
1
10-1
(1)
10-2
(2)
10-3 10
102
103
104 fi (Hz)
105
(1) Po = 10 W (2) Po = 1 W
a. VP = 25 V; RL = 16 Fig 30. Total harmonic distortion-plus-noise as a function of frequency
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TDA8933
Class-D audio amplifier
45 Gv (dB)
(1)
010aaa154
35
(2)
25
15 10
102
103
104 fi (Hz)
105
Po = 1 W (RMS) (1) VP = 17 V; RL = 8 (2) VP = 25 V; RL = 16
Fig 31. Gain as a function of frequency
100 po (%) 75
010aaa150
(2) (1)
3.0 P (W) 2.0
010aaa151
(1)
(2)
50
1.0 25
0 0 10 20 Po (W) 30
0.0 10-2
10-1
1
10 102 Po (W/channel)
po = Po / (Po + P) (1) VP = 17 V; RL = 8 ; fi = 1 kHz (2) VP = 25 V; RL = 16 ; fi = 1 kHz
Power dissipation in junction only. (1) VP = 17 V; RL = 8 ; fi = 1 kHz (2) VP = 25 V; RL = 16 ; fi = 1 kHz
Fig 32. Output power efficiency as a function of output power
Fig 33. Power dissipation as a function of output power
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TDA8933
Class-D audio amplifier
40 Po (W) 30
010aaa208
5.0 P (W) 4.0
010aaa210
(2) (1) (2)
3.0
(1)
20
(3) (4)
2.0
10 1.0
0 10 15 20 25 30 VP (P) 35
0.0 10 18 26 34 VP (V) 42
fi = 1 kHz (1) RL = 16 BTL; THD = 10 % (2) RL = 16 BTL; THD = 0.5 % (3) RL = 8 BTL; THD = 10 % (4) RL = 8 BTL; THD = 0.5 %
fi = 1 kHz; power dissipation in junction only; short time PO at THD+N = 10 % (1) RL = 8 BTL (2) RL = 16 BTL
Fig 34. Output power as a function of supply voltage
Fig 35. Power dissipation as a function of supply voltage
32 Po (W) 24
010aaa209
(2)
20 Po (W) 16
(1)
010aaa230
(1)
12 16 8
8 4
0 0 120 240 360 480 600 time (s)
0 0 150 300 450 time (s) 600
(1) VP = 25 V (2) VP = 31 V 2 layer application board (55 mm x 45 mm), 35 copper, FR4 base material in free air with natural convection.
(1) VP = 17 V
a. RL = 16 BTL; fi = 1 kHz Fig 36. Output power as a function of time
b. RL = 8 BTL; fi = 1 kHz
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TDA8933
Class-D audio amplifier
14.11 Typical application schematics (simplified)
VSSD(HW) IN1P IN1N
Cin 470 nF
Cin 470 nF
VSSA
1 2 3 4 5 6 7 8 U1 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
VSSD(HW) OSCIO HVP1 VDDP1 BOOT1 OUT1 VSSP1 STAB1 STAB2 VSSP2 OUT2 BOOT2 VDDP2 HVP2 DREF VSSD(HW)
VSSA
+ -
Cvddp 100 nF
Cvssp 100 nF
Csn 470 pF Rsn 10 LIc CIc
DIAG ENGAGE
VDD
Rbo Cbo 1 M 15 nF
VSS
MUTE CONTROL SLEEP CONTROL
Cen 470 nF
POWERUP CGND VDDA VSSA OSCREF HVPREF INREF
Cinref 100 nF
+ -
Cosc 100 nF Rosc
VDDA VSSA
TDA8933
24 23 22 21 20 19 18 17
VSSA
Cstab 100 nF
39
VSS
LIc - CIc +
Cbo 15 nF Rbo 1M
Rsn 10
TEST IN2N IN2P
Cin 470 nF
VDD
Cvddp 100 nF
VSS
Cvssp 100 nF Csn 470 pF
+ -
Cin 470 nF
VSSA
VSSD(HW)
Cdref 100 nF
VSSA
VDD
Rvdda
VDD
10
VDDA
Cvdda 100 nF Cvssa 100 nF
Cvddp 220 F/25 V
GND
Rvssa Cvssp 220 F/25 V
VSS
10
VSSA
VSS
010aaa142
Fig 37. Typical simplified application diagram for 2 x SE (symmetrical supply)
TDA8933_1
(c) NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 May 2007
40 of 47
NXP Semiconductors
TDA8933
Class-D audio amplifier
Cin 470 nF
VSSA
VSSD(HW) IN1P IN1N
1 2 3 4 5 6 7
32 31 30 29 28 27 26 U1 25 24 23 22 21 20 19 18 17
VSSD(HW) OSCIO HVP1 VDDP1 BOOT1 OUT1 VSSP1 STAB1 STAB2 VSSP2 OUT2 BOOT2 VDDP2 HVP2 DREF VSSD(HW)
VSSA
+ -
Cin 470 nF
Cvddp 100 nF
Cvssp 100 nF
Csn 470 pF
DIAG MUTE CONTROL ENGAGE
Cen 470 nF
VDD
Rbo Cbo 1 M 15 nF
VSS
Rsn 10 LIc
POWERUP CGND VDDA VSSA VDDA VSSA OSCREF HVPREF INREF
Cinref 100 nF
SLEEP CONTROL
Cosc 100 nF Rosc
CIc + - Cstab 100 nF
8 9 10 11 12 13 14 15 16
TDA8933
VSSA
39
VSS
LIc
CIc
Cbo 15 nF Rbo 1M
Rsn 10
TEST IN2N IN2P
VDD
Cvddp 100 nF
VSS
Cvssp 100 nF Csn 470 pF
VSSA VDD
Rvdda
VSSD(HW)
Cdref
VSSA
VDD GND
10
VDDA Cvdda 100 nF
Cvssa 100 nF
Cvddp 220 F/25 V
Rvssa
VSS
10
VSSA
Cvssp 220 F/25 V
VSS
010aaa141
Fig 38. Typical simplified application diagram for 1 x BTL (symmetrical supply)
TDA8933_1
(c) NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 May 2007
41 of 47
NXP Semiconductors
TDA8933
Class-D audio amplifier
VP
Rvdda
VP
10
VPA
Cvdda 100 nF Cvddp 220 F/35 V
GND
VSSD(HW)
Cin 470 nF
1 2 3 4 5 6 7 8 U1 9
32 31 30 29 28 27 26 25
VSSD(HW) OSCIO HVP1 VDDP1 BOOT1 OUT1 VSSP1 STAB1 STAB2 VSSP2 OUT2 BOOT2 VDDP2 HVP2 DREF VSSD(HW)
Cdref 100 nF Chvp 100 nF Cbo 15 nF Rbo 1M Cstab 100 nF LIc Rsn 10 CIc - + CIc Rbo Cbo 1 M 15 nF Chvp 100 nF
+ -
Cin 470 nF
IN1P IN1N DIAG ENGAGE
HVP1
Cvddp 100 nF
Csn 470pF Rsn 10
VP
MUTE CONTROL SLEEP CONTROL
Cen 470 nF
POWERUP CGND VDDA VSSA
LIc
+ -
HVP1
Cse
VPA
Cosc 100 nF Rosc 39 Chvpref 47 F/25 V Chvp 100 nF Cinref 100 nF Cin 470 nF
TDA8933
24 23 22 21 20 19 18 17
OSCREF 10 HVPREF INREF TEST IN2N IN2P 11 12 13 14 15 16
HVP2
Cse
VP
Cvddp 100 nF Csn 470 pF
+ -
Cin 470 nF
HVP2
VSSD(HW)
010aaa193
Fig 39. Typical simplified application diagram for 2 x SE (asymmetrical supply)
TDA8933_1
(c) NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 May 2007
42 of 47
NXP Semiconductors
TDA8933
Class-D audio amplifier
VP
Rvdda
VP
10
VPA
Cvdda 100 nF Cvddp 220 F/35 V
GND
VSSD(HW)
Cin 470 nF
1 2 3 4 5 6 7 8 U1 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
VSSD(HW) OSCIO HVP1 VDDP1 BOOT1 OUT1 VSSP1
Clc Chvp 100 nF Rhvp 470 Cvddp 100 nF Csn 470 pF Rsn 10
+ -
Cin 470 nF
IN1P IN1N DIAG MUTE CONTROL SLEEP CONTROL VPA ENGAGE
Cen 470 nF POWERUP
HVPREF
VP
Rbo Cbo 1 M 15 nF
LIc
CGND VDDA VSSA OSCREF HVPREF INREF
Cinref 100 nF
STAB1 STAB2 VSSP2 OUT2 BOOT2 VDDP2 HVP2 DREF VSSD(HW)
Cdref 100 nF Cbo 15 nF Rbo 1M Cstab 100 nF LIc Rsn 10 Clc
+ -
Cosc 100 nF Rosc 39
TDA8933
24 23 22 21 20 19 18 17
HVPREF
Chvp 100 nF
TEST IN2N IN2P VSSD(HW)
VP
Cvddp 100 nF Rhvp Chvp 470 100 nF Csn 470 pF
HVPREF
010aaa194
Fig 40. Typical simplified application diagram for 1 x BTL (asymmetrical supply)
TDA8933_1
(c) NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 May 2007
43 of 47
NXP Semiconductors
TDA8933
Class-D audio amplifier
15. Package outline
SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1
D
E
A X
c y HE vM A
Z 32 17
Q A2 A1 pin 1 index Lp 1 e bp 16 wM L detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 0.02 0.01 c 0.27 0.18 0.011 0.007 D (1) 20.7 20.3 0.81 0.80 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 0.419 0.394 L 1.4 Lp 1.1 0.4 Q 1.2 1.0 0.047 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.95 0.55
0.012 0.096 0.004 0.089
0.043 0.055 0.016
0.037 0.004 0.022
8o o 0
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT287-1 REFERENCES IEC JEDEC MO-119 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-08-17 03-02-19
Fig 41. Package outline SOT287-1 (SO32)
TDA8933_1 (c) NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 May 2007
44 of 47
NXP Semiconductors
TDA8933
Class-D audio amplifier
16. Revision history
Table 16. Revision history Release date 20070515 Data sheet status Preliminary data sheet Change notice Supersedes Document ID TDA8933_1
TDA8933_1
(c) NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 May 2007
45 of 47
NXP Semiconductors
TDA8933
Class-D audio amplifier
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
TDA8933_1
(c) NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 May 2007
46 of 47
NXP Semiconductors
TDA8933
Class-D audio amplifier
19. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.6 8.7 9 10 11 12 13 14 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 14.10 14.11 15 16 17 17.1 17.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mode selection and interfacing . . . . . . . . . . . . . 7 Pulse width modulation frequency . . . . . . . . . . 8 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal Foldback (TF) . . . . . . . . . . . . . . . . . . 10 OverTemperature Protection (OTP) . . . . . . . . 10 OverCurrent Protection (OCP) . . . . . . . . . . . . 10 Window Protection (WP). . . . . . . . . . . . . . . . . 10 Supply voltage protections . . . . . . . . . . . . . . . 10 Diagnostic input and output . . . . . . . . . . . . . . 12 Differential inputs . . . . . . . . . . . . . . . . . . . . . . 12 Output voltage buffers. . . . . . . . . . . . . . . . . . . 13 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 14 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal characteristics. . . . . . . . . . . . . . . . . . 18 Static characteristics. . . . . . . . . . . . . . . . . . . . 19 Dynamic characteristics . . . . . . . . . . . . . . . . . 21 Application information. . . . . . . . . . . . . . . . . . 24 Output power estimation. . . . . . . . . . . . . . . . . 24 Output current limiting. . . . . . . . . . . . . . . . . . . 26 Speaker configuration and impedance . . . . . . 26 Single-ended capacitor . . . . . . . . . . . . . . . . . . 27 Gain reduction . . . . . . . . . . . . . . . . . . . . . . . . 27 Device synchronization . . . . . . . . . . . . . . . . . . 28 Thermal behavior (printed-circuit board considerations) . . . . . . . . . . . . . . . . . . . . . . . . 29 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 29 SE curves measured in the reference design. 30 BTL curves measured in the reference design 36 Typical application schematics (simplified) . . . 40 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 44 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 45 Legal information. . . . . . . . . . . . . . . . . . . . . . . 46 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 46 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 17.3 17.4 18 19 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 46 46 47
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 May 2007 Document identifier: TDA8933_1

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